The present invention relates to a static type semiconductor memory circuit for precharging or equalizing bit lines or data input/output lines to read out data from memory cells.
In a conventional static type memory, a pair of bit lines are commonly connected to memory cells of each column, and the pair of bit lines are precharged before reading out data from the memory cells of the corresponding column.
FIG. 1 is a circuit diagram of a conventional static type memory. The memory has a memory cell MC and a sense amplifier SA1 which are commonly coupled to a pair of bit lines BL1 and BL0. The memory cell MC includes a flip-flop constituted by a series circuit of p- and n-channel MOS transistors TR1 and TR2 connected between power supply terminals VC and VS and a series circuit of p- and n-channel MOS transistors TR3 and TR4 connected between the power supply terminals VC and VS, a MOS transistor TR5 coupled between the bit line BL1 and one bistable terminal of the flip-flop, and a MOS transistor TR6 connected between the bit line BL0 and the other bistable terminal of the flip-flop.
The sense amplifier SA1 includes a transistor TR7 which is turned on or off in response to an output signal from a control signal generator 1 and which has a current path which is coupled at one end to the power supply terminal VS. SAL also includes a flip-flop constituted by a series circuit of p- and n-channel MOS transistors TR8 and TR9 connected between the other end of the current path of TR7 and the power supply terminal VC, and a series circuit of p- and n-channel MOS transistors TR10 and TR11 connected between the other end of the current path and the power supply terminal VC. The bistable terminals of the flip-flop are connected to the bit lines BL1 and BL0, respectively.
This static type memory also has a row decoder 2 for generating a row selection signal in response to row address data, and a transition detecting circuit 3 for generating an output signal TDS when it detects that the row address data has been changed.
The bit lines BL1 and BL0 are coupled to the power supply terminal VC through p-channel MOS transistors TR12 and TR13, respectively.
The operation of this static type memory will be described with reference to FIGS. 2A to 2E.
As shown in FIG. 2A, when the row address data is changed, an output signal TDS of high level is generated from the transition detecting circuit 3 for a predetermined period of time. An inverted signal TDS of the output signal TDS is supplied to the gates of the MOS transistors TR12 and TR13 so that the bit lines BL1 and BL0 are precharged through the MOS transistors TR12 and TR13 and are set at a potential corresponding to the VCC level. The control signal generator 1 generates an output signal of low level for a predetermined period of time, as shown in FIG. 2E, in response to the output signal TDS from the transition detecting circuit 3, thereby turning off the MOS transistor TR7.
When the row decoder 2 receives predetermined address data, it generates a energizing signal shown in FIG. 2F after precharging of the bit lines BL1 and BL0 is completed, so that the word line is energized. The MOS transistors TR5 and TR6 in the memory cell MC are then turned on, and one of the bit lines BL1 and BL0 starts discharging toward the reference potential level VSS, as shown in FIG. 2D, in accordance with the potentials at the bistable terminals of the flip-flop of the memory cell MC (i.e., in accordance with the content of the memory cell MC). At the discharge timing of the bit line BL1 or BL0, the control signal generator 1 generates a high level signal, as shown in FIG. 2E, to turn on the MOS transistor TR7. The sense amplifier SA is set in the operative mode. The conduction states of the MOS transistors TR8 to TR11 of the sense amplifier SA1 are determined in accordance with the potentials at the bit lines BL1 and BL0. As a result, the potential at one of the bit lines BL1 and BL0 abruptly decreases to the VSS level, as shown in FIG. 2D. A change in potential of one of the bit lines BL1 and BL0 is supplied as memory data to an external circuit.
FIG. 3 is a circuit diagram showing the detailed arrangement of the transition detecting circuit 3 shown in FIG. 1. The transition detecting circuit 3 includes N detectors 30-1 to 30-N for detecting changes in logic levels of the respective bits of the row address data, n-channel MOS transistors TR14-1 to TR14-N whose gates are respectively coupled to the output terminals of the detectors 30-1 to 30-N and whose current paths are connected in parallel with each other, a p-channel load MOS transistor TR15 whose current path is coupled at one end to the power supply terminal VC and at the other end to the reference power supply terminal VS through the MOS transistors TR14-1 to TR14-N, and an inverter 31 which has an input terminal coupled to the juncture between the MOS transistor TR15 and the MOS transistors TR14-1 to 14-N.
In this transition detecting circuit, when the row address data is changed, at least one of the detectors 30-1 to 30-N generates a high level output for a predetermined period of time. The corresponding one or ones of the MOS transistors TR14-1 to TR14-N are turned on, so that the inverter 31 generates the transition detection signal TDS of high level for the predetermined period of time.
In the static type memory shown in FIG. 1, when the row address data is changed, the transition detecting circuit 3 causes the corresponding transistor to generate the transition detection signal through the inverter. When this transition detection signal is generated, the bit lines BL1 and BL0 are precharged, so that data is read out from the memory cell MC. Data read access cannot be performed before the bit lines BL1 and BL0 are precharged. Assume that the access time from the changing of the row address data to the end of memory data access is 70 nsec. In general, it takes about 10 nsec to precharge the bit lines BL1 and BL0. Therefore, the precharge time is about 15% of the total access time. In this manner, in the conventional static type memory, the bit lines must be precharged at the initial period of the memory cycle, thereby increasing the total access time.
In addition, since a large number of memory cells are connected to the bit lines BL1 and BL0, a large load capacitance is associated with the bit lines BL1 and BL0. For this reason, in order to complete precharging operation within about 10 nsec, MOS transistors having a large current drive capacity must be used as the MOS transistors TR12 and TR13, respectively. In this case, a large peak current flows through the MOS transistors TR12 and TR13. In some cases, a current larger than 100 mA may flow through the transistors TR12 and TR13. This large current induces a current or voltage in the memory, thereby erroneously operating the memory and influencing various characteristics of the memory.
FIG. 4 shows another conventional static type memory. This memory is substantially the same as that of FIG. 1, except that a sense amplifier SA2 is used in place of the sense amplifier SA1, that a potential setting circuit PSC is used to set the potentials of data lines DL1 and DL0, and that a p-channel MOS transistor TR16 is coupled between the bit lines BL1 and BL0 and a p-channel MOS transistor TR17 is coupled between a pair of data lines DL1 and DL0. The potential setting circuit PSC has p-channel MOS transistors TR18 and TR19 coupled between a power supply terminal VC and the data lines DL1 and DL0. The sense amplifier SA2 includes n-channel MOS transistors TR20 and TR21. One end of the current path of each of the transistors TR20 and TR21 is coupled to a corresponding one of the data lines DL1 and DL0, and the other end thereof is coupled to the power supply terminal VS through an n-channel MOS transistor TR22. The gates of the MOS transisotrs TR12 and TR13 are coupled to the power supply terminal VS. An inverted signal of the transition detection signal TDS from the transition detecting circuit 3 is supplied to the gates of the MOS transistors TR16 and TR17. The gates of the MOS transistors TR20 and TR21 are coupled to the bit lines BL1 and BL0, respectively.
In this static type memory, the bit lines BL1 and BL0 are held at a potential of level "0" through the MOS transistors TR12 and TR13, respectively. The data lines DL1 and DL0 are held at a potential of "1" level through the MOS transistors TR18 and TR19, respectively, of the potential setting circuit PSC. When the row address data is updated and the transition detection signal is generated from the transition detecting circuit 3, the MOS transistors TR16 and TR17 are turned on. The potentials at the bit lines BL1 and BL0 are equalized (i.e., the potential at the bit line BL1 is made equal to that at the bit line BL0). At the same time, the potentials at the data lines DL1 and DL0 are equalized. After such initialization is completed, the MOS transistors TR16 and TR17 are turned off. In the same manner as described above, the word lines are energized by the output signal from the row decoder 2, so that the data is read out from the memory cell MC onto the bit lines BL1 and BL0. During this readout operation, the sense amplifier SA2 is set in the operative mode in response to the output signal from the control signal generator 1. As a result, the data corresponding to the readout data is supplied onto the data lines DL1 and DL0.
In the static type memory shown in FIG. 4, the potentials at the bit lines BL1 and BL0 and the potentials at the data lines DL1 and DL0 are equalized at the beginning of each readout cycle. The equalizing time cannot be neglected and increases the total access time.